1. Field of the Invention
The present invention relates to a semiconductor memory device and more particularly to a semiconductor memory device having a collective writing mode for writing data row by row.
2. Description of the Background Art
FIG. 8 is a partially omitted circuit diagram showing a structure of a conventional dynamic random access memory (hereinafter referred to as a DRAM). Such a DRAM is disclosed, for example, in Japanese Patent Laying-Open No. 63-102094.
Referring to FIG. 8, the DRAM includes a memory array MA, a sense amplifier SA, a column select gate CSG, a row decoder 101, a word driver 102, a column predecoder 103, a column decoder 104, a write circuit 105 and a read circuit 106.
Memory array MA includes a plurality of memory cells MC arranged in row and column directions, a word line WL provided corresponding to each row, and a bit line pair BL,/BL provided corresponding to each column. Well known memory cells MC are used each including an N channel MOS transistor for access and a capacitor for storing data.
Sense amplifier SA is provided corresponding to each bit line pair BL, /BL, and it amplifies a slight potential difference caused between bit lines BL, /BL according to data in selected memory cell MC when the reading operation is performed. Column select gate CSG is provided corresponding to each bit line pair BL, /BL, and it includes N channel MOS transistors 107, 108 each connected between a corresponding one of bit lines BL, /BL and a corresponding one of data input/output lines IO, I/O. Gates of N channel MOS transistors 107, 108 are connected to column decoder 104 through a column select line CSL. Row decoder 101 selects one word line WL in memory array MA. Word driver 102 raises the word line WL selected by row decoder 101 to a selected level, that is an "H level, for a prescribed time period, and activates each memory cell MC connected to the word line WL. Column predecoder 103 generates a column predecode signal in response to a column address signal CA, and supplies it to column decoder 104. Column decoder 104 raises column select line CSL designated by the column predecode signal to the selected level of "H", rendering conductive column select gate CSG corresponding to that column select line CSL.
In response to a write control signal W, write circuit 105 writes externally supplied data DI to selected memory cell MC. In response to a read control signal R, read circuit 106 outputs data DO read out of selected memory cell MC to the outside.
Here, normal operation of the DRAM will be briefly described. In the writing operation, column select line CSL designated by column address signal CA is raised to the selected "H" level by column decoder 104, rendering conductive column select gate CSG corresponding to the column select line CSL. Then, write circuit 105 raises or lowers data input/output lines IO, /IO and bit lines BL,/BL electrically connected to them to a potential according to the external data DI, that is, a power supply potential Vcc or a ground potential GND. Then, word line WL designated by row address signal RA is raised to the selected "H" level by word driver 102, activating each memory cell MC corresponding to the word line WL. The potential of bit line BL or /BL electrically connected to data input/output line IO or /IO, that is, data DI is written in the form of charges to a capacitor of activated memory cell MC.
In the reading operation, an equalize circuit, not shown, equalizes a potential of each one of bit lines BL, /BL to an intermediate potential Vcc/2 and, thereafter, word line WL designated by row address signal RA is raised to the selected "H" level by word driver 102. Thus, each memory cell MC corresponding to the word line WL is activated, and the potentials of respective bit lines BL, /BL slightly vary according to the amount of charges in the capacitor of activated memory cell MC. Then, the potentials of respective bit lines BL, /BL are amplified to power supply potential Vcc or ground potential GND by corresponding sense amplifier SA. Column select line CSL designated by column address signal CA is raised to the selected "H" Level by column decoder 104, rendering conductive column select gate CSG corresponding to the column select line CSL. The potentials of data input/output line pairs IO, /IO are converted to data DO and output to the outside by read circuit 106.
Before shipment, such a DRAM needs to be tested to see if a defective memory cell MC exists in memory array MA. However, if the test is performed by writing and reading data for each memory cell MC as described above, test time and cost are increased. Therefore, the DRAM further includes a test circuit 110 for testing by writing and reading data row by row.
As shown in FIG. 8, test circuit 110 includes a test pattern write Control terminal 111, test pattern write terminals 112, 113, an output terminal 114, a test pattern write circuit 115, a test pattern write control gate 120, a comparison circuit 123, and an OR gate 126.
Test pattern write circuit 115 includes resistors 116, 117 and inverters 118, 119. Resistors 116, 117 are connected between test pattern write terminals 112, 113 and a line of power supply potential Vcc, respectively. Inverters 118, 119 are connected between test pattern write terminals 112, 113 and nodes N118, N119, respectively. In the normal reading and writing operations, terminals 112, 113 are both driven to a floating state, and nodes N118, N119 are both at the "L" level. In the test mode, one of terminals 112, 113 is supplied with the "L" level and one of nodes N118, N119 attains the "H" level.
Test pattern write control gate 120 is provided corresponding to each bit line pair BL, /BL, and it includes a pair of N channel MOS transistors 121, 122. N channel MOS transistors 121, 122 are connected between nodes N119, N118 and bit lines BL, /BL, respectively, and their gates are both connected to test pattern write control terminal 111. In the normal reading and writing operations, terminal 111 is supplied with the "L" level and N channel MOS transistors 121, 122 are rendered non-conductive. When the writing operation is performed in the test mode, terminal 111 is supplied with the "H" level, and N channel MOS transistors 121, 122, node N119 and all bit lines BL, as well as node N119 and all bit lines are rendered conductive.
Comparison circuit 123 is provided corresponding to each bit line pair BL, /BL, and it includes a pair of N channel MOS transistors 124, 125. N channel MOS transistors 124, 125 are connected between a node N123 and nodes N119, N118, respectively, and their gates are connected to a corresponding one of bit lines BL, /BL. During the reading operation in the test mode, one of test pattern write terminals 112, 113, other than the one which was supplied with the "L" level during the writing operation in the test mode, is supplied with the "L" level.
For example, if the "L" level is supplied to terminal 112 and the "H" level is supplied to bit line /BL during the writing operation in the test mode, bit line /BL is at the "H" level and N channel MOS transistor 125 is rendered conductive during the reading operation in test mode as well, provided that memory cells MC are normal. At this time, since the "L" level is supplied not to terminal 112 but to terminal 113 and node N118 is at the "L" level, output node N123 of comparison circuit 123 is at the "L" level. If memory cell MC is defective, bit line BL is at the "H" level and N channel MOS transistor 124 is rendered conductive during the reading operation in the test mode. Since the "L" level is supplied not to terminal 112 but to terminal 113 and node N119 attains to the "H" level at this time, output node 123 of comparison circuit 123 is also at the "H" level.
OR gate 126 includes an N channel MOS transistor 127 provided corresponding to each bit line pair BL, /BL, an N channel MOS transistor 128, and an inverter 129. N channel MOS transistor 127 is connected between a node N128 and the line of ground potential GND, and its gate is connected to output node N123 of corresponding comparison circuit 123. N channel MOS transistor 128 is connected between the line of power supply potential Vcc and node N128, and its gate receives a precharge signal .phi.p. Inverter 129 is connected between node N128 and an output terminal 114 of test circuit 110.
First, precharge signal .phi.p attains the "H" level for a prescribed time period and N channel MOS transistor 128 is rendered conductive, charging node N128 to the "H" level. When at least one output node N123 of comparison circuit 123 attains the "H" level, N channel MOS transistor 127 corresponding to the output node N123 is rendered conductive to discharge node N128 to the "L" level, and inverter 129 outputs an "H" level signal indicating the existence of a defective memory cell MC to output terminal 114.
Next, operation of the DRAM in the test mode will be briefly described. During the reading operation in the test mode, the "H" level is supplied to test pattern write control terminal 111, and test pattern write control gate 120 is rendered conductive, rendering conductive the paths between node N119 and all bit lines BL as well as node N118 and all bit lines /BL. One of test pattern write terminals 112, 113 is supplied with the "L" level, and one of bit lines BL, /BL is supplied with the "H" level and the other with the "L" level. Then, word line WL designated by row address signal RA is raised to the selected "H" level by word driver 102. Thus, all memory cells MC corresponding to that word line WL are activated and the same data is collectively written to each memory cell MC.
During the reading operation in the test mode, the inactive, that is, the "L" level is supplied to test pattern write control terminal 111, and test pattern write control gate 120 is rendered non-conductive, rendering conductive the paths between node N119 and bit line BL as well node N118 and bit line /BL. The "L" level is supplied to one of terminals 112, 113, other than the one which was supplied with the "L" level during the writing operation in the test mode, and word line WL designated by row address signal RA is raised to the selected "H" level by word driver 102, thus data of all memory cells MC corresponding to that word line WL is read out. If there should be any defective memory cell MC in those memory cells MC, output node N123 of comparison circuit 123 corresponding to the defective memory cell MC attains the "H" level, and node N128 is discharged to the "L" level, driving output terminal 114 to the "H" level. If all memory cells MC are normal, output nodes N123 of all comparison circuits 123 are at the "L" level and node N128 is kept precharged to the "H" level without being discharged, thus output terminal 114 is at the "L" level. Therefore, by detecting the level of output terminal 114, a determination can be made if a defective memory cell MC exists in each row. A row containing the defective memory cell MC is replaced by a spare row, not shown.
However, a conventional DRAM needs to be separately provided with test pattern write circuit 115, test pattern write control gate 120 and so on, in order to collectively write data row by row. Thus, it has a problem of increased layout area.